1. Field of the Invention
The invention relates generally to integrated circuits and more specifically relates to correlating test signals acquired from multiple circuitry blocks of an integrated circuit.
2. Related Patents
This patent is related to commonly owned U.S. patent application Ser. No. 13/434,940 entitled “METHODS AND STRUCTURE FOR CORRELATING MULTIPLE TEST OUTPUTS OF AN INTEGRATED CIRCUIT ACQUIRED DURING SEPARATE INSTANCES OF AN EVENT” which is hereby incorporated by reference.
3. Discussion of Related Art
Electronic circuits perform a wide variety of designated functions for electronic systems. For example, integrated circuits may be used for data processing, data storage and retrieval, system analysis and control, and many other functions. Integrated circuits may be subject to programming, design, or operational errors, and internal operational signals are not exposed for acquisition by external devices during normal operation (i.e., they are internal to the circuit). It would be impractical or impossible to connect every internal operational signal to its own dedicated output pin of the circuit for monitoring purposes. As such, it is desirable not only to include logic in the circuit that performs the circuit's desired function, but also to include logic and components at the circuit for acquiring selected internal signals for debugging and testing purposes (e.g., for externally monitoring internal operational signals of the circuit). For example, the circuit may include test multiplexers (MUXs) having registers that can be programmed to select internal operational signals for routing through the test MUXs. The test MUXs provide the selected internal operational signals as test outputs (e.g., specialized debug outputs) for the circuit. Utilizing MUXs to output test signals that are normally internal to the circuit ensures that the cost and size of a circuit implementing testing logic is reduced, because MUXs allow a large number of internal signaling pathways to be condensed into a much smaller number of output signal paths. These output paths may be monitored by a logic analyzer so as to acquire the selected internal operational signals.
Unfortunately, utilizing a test signal selection hierarchy for routing internal operational signals to an output results in a number of problems. For example, because routing elements for the circuit may be located in physically distant locations from each other within the integrated circuit die, each routing path to a final output varies in length, the number of routing components, and the type of routing components. Thus, signaling pathways used to route internal operational signals from each circuitry block may be associated with a different routing delay. This causes a substantial problem when attempting to analyze received signals, as signals that were generated at the same time in different circuit blocks (or even in the same circuit block) may appear to be asynchronous as-received at the final output. In the field of circuit testing, it may be critical to measure the exact response of an internal operational signal to a stimulus. Thus, even relatively small delays between received signals may alter the way that the data is interpreted, causing a designer to misdiagnose problems at the circuit.
Thus it is an ongoing challenge to acquire internal operational signals for use in testing a circuit without altering the timing of those signals with respect to each other.